FCVTN, FCVTN2 (FP32 to FP8) -- A64

Single-precision to 8-bit floating-point convert and narrow (vector). This instruction converts each single-precision element of the two source vectors to 8-bit floating-point while scaling the value by 2^{SInt(FPMR.NSCALE)}, and places the in-order results in the 8-bit elements of the lower or upper half of the destination vector. FCVTN writes the results to the lower half of the destination vector and clears the upper half. FCVTN2 writes the results to the upper half of the destination vector without affecting the other bits of the vector.

Advanced SIMD
(FEAT_FP8)

if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer part = UInt(Q); constant integer elements = 128 DIV 32;

Assembler Symbols

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:

Q	2
0	[absent]
1	[present]

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in Q:

Q	<Ta>
0	8B
1	16B

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>	Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64(); bits(128) operand1 = V[n, 128]; bits(128) operand2 = V[m, 128]; bits(64) result; for e = 0 to elements-1 Elem[result, 0*elements+e, 8] = FPConvertFP8(Elem[operand1, e, 32], FPCR, FPMR, 8); Elem[result, 1*elements+e, 8] = FPConvertFP8(Elem[operand2, e, 32], FPCR, FPMR, 8); Vpart[d, part, 64] = result;

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	0	0	1	1	1	0	0	0	0	Rm					1	1	1	1	0	1	Rn					Rd
		U						size									opcode