Single-precision convert, narrow and interleave to 8-bit floating-point (bottom)
Convert each single-precision element of the group of two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and place the two-way interleaved results in the corresponding even-numbered 8-bit elements of the destination vector, zeroing the odd-numbered elements. The 8-bit floating-point encoding format is selected by FPMR.F8D.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Zn | 0 | Zd | |||||||
| T | |||||||||||||||||||||||||||||||
if (!HaveSVE2() && !HaveSME2()) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; integer n = UInt(Zn:'0'); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
CheckFPMREnabled(); CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; bits(VL) result; bits(VL) operand1 = Z[n+0, VL]; bits(VL) operand2 = Z[n+1, VL]; for e = 0 to elements-1 bits(32) element1 = Elem[operand1, e, 32]; bits(32) element2 = Elem[operand2, e, 32]; bits(8) res1 = FPConvertFP8(element1, FPCR, FPMR, 8); bits(8) res2 = FPConvertFP8(element2, FPCR, FPMR, 8); Elem[result, 2*e + 0, 16] = ZeroExtend(res1, 16); Elem[result, 2*e + 1, 16] = ZeroExtend(res2, 16); Z[d, VL] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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