FMLAL (multiple vectors, FP8 to FP16)

Multi-vector 8-bit floating-point multiply-add long to half-precision

This 8-bit floating-point multiply-add long instruction widens all 8-bit floating-point elements in the two or four first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2^{-UInt(FPMR.LSCALE[3:0])} before being destructively added without intermediate rounding to the overlapping 16-bit half-precision elements of the ZA double-vector groups.

The lowest of the two consecutive vector numbers forming the double-vector group within each half of or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors. The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

This instruction is unpredicated.

It has encodings from 2 classes: Two ZA double-vectors and Four ZA double-vectors

Two ZA double-vectors
(FEAT_SME_F8F16)

if !IsFeatureImplemented(FEAT_SME_F8F16) then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'0'); integer m = UInt(Zm:'0'); integer offset = UInt(off2:'0'); constant integer nreg = 2;

Four ZA double-vectors
(FEAT_SME_F8F16)

if !IsFeatureImplemented(FEAT_SME_F8F16) then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'00'); integer m = UInt(Zm:'00'); integer offset = UInt(off2:'0'); constant integer nreg = 4;