FMLALL (multiple vectors)

Multi-vector 8-bit floating-point multiply-add long-long to single-precision

This 8-bit floating-point multiply-add long long instruction widens all 8-bit floating-point elements in the two or four first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2^{-UInt(FPMR.LSCALE)} before being destructively added without intermediate rounding to the overlapping 32-bit single-precision elements of the ZA quad-vector groups.

The lowest of the four consecutive vector numbers forming the quad-vector group within each half of or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors. The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

This instruction is unpredicated.

It has encodings from 2 classes: Two ZA quad-vectors and Four ZA quad-vectors

Two ZA quad-vectors
(FEAT_SME_F8F32)

if !IsFeatureImplemented(FEAT_SME_F8F32) then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'0'); integer m = UInt(Zm:'0'); integer offset = UInt(o1:'00'); constant integer nreg = 2;

Four ZA quad-vectors
(FEAT_SME_F8F32)

if !IsFeatureImplemented(FEAT_SME_F8F32) then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'00'); integer m = UInt(Zm:'00'); integer offset = UInt(o1:'00'); constant integer nreg = 4;