Multi-vector floating-point fused multiply-subtract by indexed element
Multiply the indexed element of the second source vector by the corresponding floating-point elements of the two or four first source vectors and destructively subtract without intermediate rounding from the corresponding elements of the ZA single-vector groups.
The elements within the second source vector are specified using an immediate element index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 1 to 2 bits depending on the size of the element. The vector numbers forming the single-vector group within each half of or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction follows SME ZA-targeting floating-point behaviors.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.F64F64 indicates whether the double-precision variant is implemented, and ID_AA64SMFR0_EL1.F16F16 indicates whether the half-precision variant is implemented.
It has encodings from 6 classes: Two ZA single-vectors of half precision elements , Two ZA single-vectors of single precision elements , Two ZA single-vectors of double precision elements , Four ZA single-vectors of half precision elements , Four ZA single-vectors of single precision elements and Four ZA single-vectors of double precision elements
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 0 | Rv | 1 | i3h | Zn | 0 | 1 | i3l | off3 | ||||||||||
S |
if !HaveSME2() || !IsFeatureImplemented(FEAT_SME_F16F16) then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 16; integer n = UInt(Zn:'0'); integer m = UInt('0':Zm); integer offset = UInt(off3); integer index = UInt(i3h:i3l); boolean sub_op = TRUE; constant integer nreg = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Zm | 0 | Rv | 0 | i2 | Zn | 0 | 1 | 0 | off3 | ||||||||||
S |
if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 32; integer n = UInt(Zn:'0'); integer m = UInt('0':Zm); integer offset = UInt(off3); integer index = UInt(i2); boolean sub_op = TRUE; constant integer nreg = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | Zm | 0 | Rv | 0 | 0 | i1 | Zn | 0 | 1 | 0 | off3 | |||||||||
S |
if !(HaveSME2() && HaveSMEF64F64()) then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 64; integer n = UInt(Zn:'0'); integer m = UInt('0':Zm); integer offset = UInt(off3); integer index = UInt(i1); boolean sub_op = TRUE; constant integer nreg = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 1 | Rv | 1 | i3h | Zn | 0 | 0 | 1 | i3l | off3 | |||||||||
S |
if !HaveSME2() || !IsFeatureImplemented(FEAT_SME_F16F16) then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 16; integer n = UInt(Zn:'00'); integer m = UInt('0':Zm); integer offset = UInt(off3); integer index = UInt(i3h:i3l); boolean sub_op = TRUE; constant integer nreg = 4;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Zm | 1 | Rv | 0 | i2 | Zn | 0 | 0 | 1 | 0 | off3 | |||||||||
S |
if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 32; integer n = UInt(Zn:'00'); integer m = UInt('0':Zm); integer offset = UInt(off3); integer index = UInt(i2); boolean sub_op = TRUE; constant integer nreg = 4;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | Zm | 1 | Rv | 0 | 0 | i1 | Zn | 0 | 0 | 1 | 0 | off3 | ||||||||
S |
if !(HaveSME2() && HaveSMEF64F64()) then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 64; integer n = UInt(Zn:'00'); integer m = UInt('0':Zm); integer offset = UInt(off3); integer index = UInt(i1); boolean sub_op = TRUE; constant integer nreg = 4;
<Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
<offs> |
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. |
<Zn4> |
Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3. |
<Zn2> |
Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1. |
<Zm> |
Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. |
CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; integer vectors = VL DIV 8; integer vstride = vectors DIV nreg; integer eltspersegment = 128 DIV esize; bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; for r = 0 to nreg-1 bits(VL) operand1 = Z[n+r, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) operand3 = ZAvector[vec, VL]; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; integer segmentbase = e - (e MOD eltspersegment); integer s = segmentbase + index; bits(esize) element2 = Elem[operand2, s, esize]; bits(esize) element3 = Elem[operand3, e, esize]; if sub_op then element1 = FPNeg(element1, FPCR); Elem[result, e, esize] = FPMulAdd_ZA(element3, element1, element2, FPCR); ZAvector[vec, VL] = result; vec = vec + vstride;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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