FMLSL (multiple and single vector)

Multi-vector floating-point multiply-subtract long by vector

This half-precision floating-point multiply-subtract long instruction widens all 16-bit half-precision elements in the one, two, or four first source vectors and the second source vector to single-precision format, then multiplies the corresponding elements and destructively subtracts these values without intermediate rounding from the overlapping 32-bit single-precision elements of the ZA double-vector groups. The lowest of the two consecutive vector numbers forming the double-vector group within all of, each half of, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction follows SME ZA-targeting floating-point behaviors.

This instruction is unpredicated.

It has encodings from 3 classes: One ZA double-vector , Two ZA double-vectors and Four ZA double-vectors

One ZA double-vector
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(off3:'0'); boolean sub_op = TRUE; constant integer nreg = 1;

Two ZA double-vectors
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(off2:'0'); boolean sub_op = TRUE; constant integer nreg = 2;

Four ZA double-vectors
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(off2:'0'); boolean sub_op = TRUE; constant integer nreg = 4;