Floating-point Move to or from general-purpose register without conversion. This instruction transfers the contents of a SIMD&FP register to a general-purpose register, or the contents of a general-purpose register to a SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | x | 1 | 1 | x | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | |||||||||
S | rmode | opcode |
if ftype == '10' && opcode<2:1>:rmode != '11 01' then UNDEFINED; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer intsize = 32 << UInt(sf); constant integer decode_fltsize = if ftype == '10' then 64 else (8 << UInt(ftype EOR '10')); FPConvOp op; FPRounding rounding; boolean unsigned; integer part; case opcode<2:1>:rmode of when '00 xx' // FCVT[NPMZ][US] rounding = FPDecodeRounding(rmode); unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI; when '01 00' // [US]CVTF rounding = FPRoundingMode(FPCR); unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_ItoF; when '10 00' // FCVTA[US] rounding = FPRounding_TIEAWAY; unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI; when '11 00' // FMOV if decode_fltsize != 16 && decode_fltsize != intsize then UNDEFINED; op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; part = 0; when '11 01' // FMOV D[1] if intsize != 64 || ftype != '10' then UNDEFINED; op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; part = 1; when '11 11' // FJCVTZS if !IsFeatureImplemented(FEAT_JSCVT) then UNDEFINED; rounding = FPRounding_ZERO; unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI_JS; otherwise UNDEFINED;
<Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Dn> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
if op == FPConvOp_CVT_FtoI_JS then CheckFPAdvSIMDEnabled64(); else CheckFPEnabled64(); constant boolean merge = IsMerging(FPCR); constant integer fltsize = if op == FPConvOp_CVT_ItoF && merge then 128 else decode_fltsize; bits(fltsize) fltval; bits(intsize) intval; case op of when FPConvOp_CVT_FtoI fltval = V[n, fltsize]; intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding, intsize); X[d, intsize] = intval; when FPConvOp_CVT_ItoF intval = X[n, intsize]; fltval = if merge then V[d, fltsize] else Zeros(fltsize); Elem[fltval, 0, decode_fltsize] = FixedToFP(intval, 0, unsigned, FPCR, rounding, decode_fltsize); V[d, fltsize] = fltval; when FPConvOp_MOV_FtoI fltval = Vpart[n, part, fltsize]; intval = ZeroExtend(fltval, intsize); X[d, intsize] = intval; when FPConvOp_MOV_ItoF intval = X[n, intsize]; fltval = intval<fltsize-1:0>; Vpart[d, part, fltsize] = fltval; when FPConvOp_CVT_FtoI_JS bit z; fltval = V[n, fltsize]; (intval, z) = FPToFixedJS(fltval, FPCR, intsize); PSTATE.<N,Z,C,V> = '0':z:'00'; X[d, intsize] = intval;
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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