Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for the source SIMD&FP register and writes the result to the destination SIMD&FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Half-precision and Single-precision and double-precision
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| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | Rn | Rd | ||||||||
| U | a | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16;
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| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | sz | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | Rn | Rd | ||||||||
| U | opcode | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 32 << UInt(sz);
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Hn> |
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPEnabled64(); bits(esize) operand = V[n, esize]; boolean merge = IsMerging(FPCR); bits(128) result = if merge then V[d, 128] else Zeros(128); Elem[result, 0, esize] = FPRecpX(operand, FPCR); V[d, 128] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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