Floating-point adjust exponent by vector. This instruction multiplies the floating-point elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector, and places the results in the corresponding elements of the destination vector.
It has encodings from 2 classes: Half-precision and Single-precision and double-precision
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| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | Rm | 0 | 0 | 1 | 1 | 1 | 1 | Rn | Rd | ||||||||||||
| U | a | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer esize = 16; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; constant integer elements = datasize DIV esize;
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| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | x | 1 | Rm | 1 | 1 | 1 | 1 | 1 | 1 | Rn | Rd | ||||||||||||
| U | size | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; if Q == '0' && size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; constant integer elements = datasize DIV esize;
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; for e = 0 to elements-1 bits(esize) op1 = Elem[operand1, e, esize]; integer op2 = SInt(Elem[operand2, e, esize]); Elem[result, e, esize] = FPScale(op1, op2, FPCR); V[d, datasize] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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