Guarded Control Stack Store stores a doubleword from a register to memory. The address that is used for the store is calculated from a base register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | Rn | Rt | ||||||||
| opc | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_GCS) then UNDEFINED; integer n = UInt(Rn); integer t = UInt(Rt);
| <Xt> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(64) data; bits(2) effective_el = PSTATE.EL; if effective_el == PSTATE.EL then CheckGCSSTREnabled(); AccessDescriptor accdesc = CreateAccDescGCS(effective_el, MemOp_STORE); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = X[t, 64]; Mem[address, 8, accdesc] = data;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.