Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.
This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This instruction is used by the alias MOV (from general).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 1 | 1 | 1 | Rn | Rd | ||||||||||||
| Q | op | imm4 | |||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); constant integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer esize = 8 << size;
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Ts> |
Is an element size specifier,
encoded in
|
| <index> |
Is the element index
encoded in
|
| <R> |
Is the width specifier for the general-purpose source register,
encoded in
|
| <n> |
Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(esize) element = X[n, esize]; bits(128) result; result = V[d, 128]; Elem[result, index, esize] = element; V[d, 128] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.