Contiguous load of bytes to multiple consecutive vectors (immediate index)
Contiguous load of unsigned bytes to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address.
Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
It has encodings from 2 classes: Two registers and Four registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | imm4 | 0 | 0 | 0 | PNg | Rn | Zt | 0 | ||||||||||||
msz<1> | msz<0> | N |
if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; integer n = UInt(Rn); integer g = UInt('1':PNg); constant integer nreg = 2; integer t = UInt(Zt:'0'); constant integer esize = 8; integer offset = SInt(imm4);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | imm4 | 1 | 0 | 0 | PNg | Rn | Zt | 0 | 0 | |||||||||||
msz<1> | msz<0> | N |
if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; integer n = UInt(Rn); integer g = UInt('1':PNg); constant integer nreg = 4; integer t = UInt(Zt:'00'); constant integer esize = 8; integer offset = SInt(imm4);
<Zt4> |
Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3. |
<Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1. |
<PNg> |
Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
if HaveSVE2p1() then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant integer mbytes = esize DIV 8; bits(64) base; bits(PL) pred = P[g, PL]; bits(PL * nreg) mask = CounterToPredicate(pred<15:0>, PL * nreg); array [0..3] of bits(VL) values; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = n != 31; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; for r = 0 to nreg-1 for e = 0 to elements-1 if ActivePredicateElement(mask, r * elements + e, esize) then integer eoff = offset * nreg * elements + r * elements + e; bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc); Elem[values[r], e, esize] = Mem[addr, mbytes, accdesc]; else Elem[values[r], e, esize] = Zeros(esize); for r = 0 to nreg-1 Z[t+r, VL] = values[r];
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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