Contiguous load of halfwords to 16-bit element ZA tile slice
The slice number within the tile is selected by the sum of the slice index register and immediate offset, modulo the number of 16-bit elements in a vector. The immediate offset is in the range 0 to 7. The memory address is generated by a 64-bit scalar base and an optional 64-bit scalar offset which is multiplied by 2 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Rm | V | Rs | Pg | Rn | 0 | ZAt | off3 | |||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !HaveSME() then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt('0':Pg); integer s = UInt('011':Rs); integer t = UInt(ZAt); integer offset = UInt(off3); constant integer esize = 16; boolean vertical = V == '1';
| <ZAt> |
Is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAt" field. |
| <HV> |
Is the horizontal or vertical slice indicator,
encoded in
|
| <Ws> |
Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field. |
| <offs> |
Is the slice index offset, in the range 0 to 7, encoded in the "off3" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer dim = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g, PL]; bits(64) moffs = X[m, 64]; bits(32) index = X[s, 32]; integer slice = (UInt(index) + offset) MOD dim; bits(VL) result; constant integer mbytes = esize DIV 8; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = TRUE; AccessDescriptor accdesc = CreateAccDescSME(MemOp_LOAD, nontemporal, contiguous, tagchecked); if n == 31 then if AnyActiveElement(mask, esize) || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; for e = 0 to dim - 1 addr = GenerateAddress(base, UInt(moffs) * mbytes, accdesc); if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = Mem[addr, mbytes, accdesc]; else Elem[result, e, esize] = Zeros(esize); moffs = moffs + 1; ZAslice[t, esize, vertical, slice, VL] = result;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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