Load Pair of SIMD&FP registers. This instruction loads a pair of SIMD&FP registers from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
boolean wback = TRUE; boolean postindex = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
boolean wback = TRUE; boolean postindex = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
boolean wback = FALSE; boolean postindex = FALSE;
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDP (SIMD&FP).
| <St1> |
Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <St2> |
Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Dt1> |
Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Dt2> |
Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Qt1> |
Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Qt2> |
Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); if opc == '11' then UNDEFINED; integer scale = 2 + UInt(opc); constant integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale); boolean tagchecked = wback || n != 31; boolean rt_unknown = FALSE; if t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();
CheckFPEnabled64(); bits(64) address; bits(64) address2; bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, FALSE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = GenerateAddress(address, offset, accdesc); address2 = GenerateAddress(address, dbytes, accdesc); data1 = Mem[address, dbytes, accdesc]; data2 = Mem[address2, dbytes, accdesc]; if rt_unknown then data1 = bits(datasize) UNKNOWN; data2 = bits(datasize) UNKNOWN; V[t, datasize] = data1; V[t2, datasize] = data2; if wback then if postindex then address = GenerateAddress(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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