integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); bits(64) offset = LSL(SignExtend(imm7, 64), 2); boolean tagchecked = wback || n != 31; boolean rt_unknown = FALSE; boolean wb_unknown = FALSE; if wback && (t == n || t2 == n) && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

bits(64) address; bits(64) address2; bits(32) data1; bits(32) data2; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = GenerateAddress(address, offset, accdesc); address2 = GenerateAddress(address, 4, accdesc); data1 = Mem[address, 4, accdesc]; data2 = Mem[address2, 4, accdesc]; if rt_unknown then data1 = bits(32) UNKNOWN; data2 = bits(32) UNKNOWN; X[t, 64] = SignExtend(data1, 64); X[t2, 64] = SignExtend(data2, 64); if wback then if wb_unknown then address = bits(64) UNKNOWN; elsif postindex then address = GenerateAddress(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;