LDR (immediate, SIMD&FP) -- A64

Load SIMD&FP Register (immediate offset). This instruction loads an element from memory, and writes the result as a scalar to the SIMD&FP register. The address that is used for the load is calculated from a base register value, a signed immediate offset, and an optional offset that is a multiple of the element size.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Post-index

boolean wback = TRUE; boolean postindex = TRUE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);

Pre-index

boolean wback = TRUE; boolean postindex = FALSE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);

Unsigned offset

boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = LSL(ZeroExtend(imm12, 64), scale);

Assembler Symbols

<Bt>	Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<Ht>	Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<St>	Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt>	Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<pimm>	For the 8-bit variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
	For the 16-bit variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.
	For the 32-bit variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
	For the 64-bit variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.
	For the 128-bit variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); MemOp memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; constant integer datasize = 8 << scale; boolean tagchecked = memop != MemOp_PREFETCH && (wback || n != 31);

Operation

CheckFPEnabled64(); bits(64) address; bits(datasize) data; AccessDescriptor accdesc = CreateAccDescASIMD(memop, FALSE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = GenerateAddress(address, offset, accdesc); case memop of when MemOp_STORE data = V[t, datasize]; Mem[address, datasize DIV 8, accdesc] = data; when MemOp_LOAD data = Mem[address, datasize DIV 8, accdesc]; V[t, datasize] = data; if wback then if postindex then address = GenerateAddress(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46