Load vector register
Load a vector register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current vector register size in bytes. This instruction is unpredicated.
The load is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm9h | 0 | 1 | 0 | imm9l | Rn | Zt | |||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer imm = SInt(imm9h:imm9l);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 8; bits(64) base; integer offset = imm * elements; bits(VL) result; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = n != 31; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; bits(64) addr = GenerateAddress(base, offset, accdesc); boolean aligned = IsAligned(addr, 16); if !aligned && AlignmentEnforced() then AArch64.Abort(addr, AlignmentFault(accdesc)); for e = 0 to elements-1 Elem[result, e, 8] = AArch64.MemSingle[addr, 1, accdesc, aligned]; offset = offset + 1; addr = GenerateAddress(base, offset, accdesc); Z[t, VL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.