Load SIMD&FP Register (unscaled offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
size | 1 | 1 | 1 | 1 | 0 | 0 | x | 1 | 0 | imm9 | 0 | 0 | Rn | Rt | |||||||||||||||||
VR | opc |
integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);
<Bt> |
Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<simm> |
Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field. |
<Ht> |
Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<St> |
Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Dt> |
Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Qt> |
Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
integer n = UInt(Rn); integer t = UInt(Rt); MemOp memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; constant integer datasize = 8 << scale; boolean tagchecked = memop != MemOp_PREFETCH && (n != 31);
CheckFPEnabled64(); bits(64) address; bits(datasize) data; AccessDescriptor accdesc = CreateAccDescASIMD(memop, FALSE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = GenerateAddress(address, offset, accdesc); case memop of when MemOp_STORE data = V[t, datasize]; Mem[address, datasize DIV 8, accdesc] = data; when MemOp_LOAD data = Mem[address, datasize DIV 8, accdesc]; V[t, datasize] = data;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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