Load Exclusive Pair of Registers derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | sz | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | (1) | (1) | (1) | (1) | (1) | 0 | Rt2 | Rn | Rt | ||||||||||||
| L | Rs | o0 | |||||||||||||||||||||||||||||
integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); constant integer elsize = 32 << UInt(sz); constant integer datasize = elsize * 2; boolean tagchecked = n != 31; boolean rt_unknown = FALSE; if t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDXP.
| <Wt1> |
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Wt2> |
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
bits(64) address; bits(datasize) data; constant integer dbytes = datasize DIV 8; AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_LOAD, FALSE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; // Tell the Exclusives monitors to record a sequence of one or more atomic // memory reads from virtual address range [address, address+dbytes-1]. // The Exclusives monitor will only be set if all the reads are from the // same dbytes-aligned physical address, to allow for the possibility of // an atomicity break if the translation is changed between reads. AArch64.SetExclusiveMonitors(address, dbytes); if rt_unknown then // ConstrainedUNPREDICTABLE case X[t, datasize] = bits(datasize) UNKNOWN; // In this case t = t2 elsif elsize == 32 then // 32-bit load exclusive pair (atomic) data = Mem[address, dbytes, accdesc]; if BigEndian(accdesc.acctype) then X[t, datasize-elsize] = data<datasize-1:elsize>; X[t2, elsize] = data<elsize-1:0>; else X[t, elsize] = data<elsize-1:0>; X[t2, datasize-elsize] = data<datasize-1:elsize>; else // elsize == 64 // 64-bit load exclusive pair (not atomic), but must be 128-bit aligned if !IsAligned(address, dbytes) then AArch64.Abort(address, AlignmentFault(accdesc)); bits(64) address2 = GenerateAddress(address, 8, accdesc); X[t, 64] = Mem[address, 8, accdesc]; X[t2, 64] = Mem[address2, 8, accdesc];
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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