LUTI4 (four registers, 8-bit)

Copy 8-bit elements from ZT0 to four destination vectors using packed 4-bit indices in the two source vectors.

if !HaveSME2() || !IsFeatureImplemented(FEAT_SME_LUTv2) then UNDEFINED; if size != '00' then UNDEFINED; constant integer esize = 8 << UInt(size); integer isize = 4; integer n = UInt(Zn:'0'); integer dstride = 1; integer d = UInt(Zd:'00'); constant integer nreg = 4;

Strided
(FEAT_SME_LUTv2)

if !HaveSME2p1() || !IsFeatureImplemented(FEAT_SME_LUTv2) then UNDEFINED; if size != '00' then UNDEFINED; constant integer esize = 8 << UInt(size); integer isize = 4; integer n = UInt(Zn:'0'); integer dstride = 4; integer d = UInt(D:'00':Zd); constant integer nreg = 4;

Assembler Symbols

<Zd1>	For the consecutive variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.
	For the strided variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

<Zd4>	For the consecutive variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.
	For the strided variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

Operation

CheckStreamingSVEEnabled(); CheckSMEZT0Enabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; bits(2*VL) indexes = Z[n+1, VL] : Z[n+0, VL]; bits(512) table = ZT0[512]; for r = 0 to nreg-1 integer base = r * elements; bits(VL) result; for e = 0 to elements-1 integer index = UInt(Elem[indexes, base+e, isize]); Elem[result, e, esize] = Elem[table, index, 32]<esize-1:0>; Z[d, VL] = result; d = d + dstride;

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46