MADD -- A64

Multiply-Add multiplies two register values, adds a third register value, and writes the result to the destination register.

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer a = UInt(Ra); constant integer destsize = 32 << UInt(sf);

Assembler Symbols

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>	Is the 32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Wm>	Is the 32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

<Wa>	Is the 32-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>	Is the 64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Xm>	Is the 64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

<Xa>	Is the 64-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.

Alias Conditions

Alias	Is preferred when
MUL	Ra == '11111'

Operation

bits(destsize) operand1 = X[n, destsize]; bits(destsize) operand2 = X[m, destsize]; bits(destsize) operand3 = X[a, destsize]; integer result; result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); X[d, destsize] = result<destsize-1:0>;

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
sf	0	0	1	1	0	1	1	0	0	0	Rm					0	Ra					Rn					Rd
	op54							op31								o0

MADD

32-bit (sf == 0)

64-bit (sf == 1)

Assembler Symbols

Alias Conditions

Operation

Operational information