MOVA (tile to vector, two registers)

The instruction operates on two consecutive horizontal or vertical slices within a named ZA tile of the specified element size.

The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 2 in the range 0 to the number of elements in a 128-bit vector segment minus 2.

8-bit
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 2; constant integer esize = 8; integer d = UInt(Zd:'0'); integer n = 0; integer offset = UInt(off3:'0'); boolean vertical = V == '1';

16-bit
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 2; constant integer esize = 16; integer d = UInt(Zd:'0'); integer n = UInt(ZAn); integer offset = UInt(off2:'0'); boolean vertical = V == '1';

32-bit
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 2; constant integer esize = 32; integer d = UInt(Zd:'0'); integer n = UInt(ZAn); integer offset = UInt(o1:'0'); boolean vertical = V == '1';

64-bit
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 2; constant integer esize = 64; integer d = UInt(Zd:'0'); integer n = UInt(ZAn); integer offset = 0; boolean vertical = V == '1';

Assembler Symbols

<Zd1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<ZAn>	For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAn" field.
	For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAn" field.
	For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAn" field.

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V	<HV>
0	H
1	V

<Ws>	Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs1>	For the 8-bit variant: is the first slice index offset, encoded as "off3" field times 2.
	For the 16-bit variant: is the first slice index offset, encoded as "off2" field times 2.
	For the 32-bit variant: is the first slice index offset, encoded as "o1" field times 2.
	For the 64-bit variant: is the first slice index offset, with implicit value 0.

<offs2>	For the 8-bit variant: is the second slice index offset, encoded as "off3" field times 2 plus 1.
	For the 16-bit variant: is the second slice index offset, encoded as "off2" field times 2 plus 1.
	For the 32-bit variant: is the second slice index offset, encoded as "o1" field times 2 plus 1.
	For the 64-bit variant: is the second slice index offset, with implicit value 1.

Operation

CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; if nreg == 4 && esize == 64 && VL < 256 then UNDEFINED; integer slices = VL DIV esize; bits(32) index = X[s, 32]; integer slice = ((UInt(index) - (UInt(index) MOD nreg)) + offset) MOD slices; for r = 0 to nreg-1 bits(VL) result = ZAslice[n, esize, vertical, slice + r, VL]; Z[d + r, VL] = result;

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	0	V	Rs		0	0	0	0	0	off3			Zd				0
								size<1>	size<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	0	1	0	0	0	1	1	0	V	Rs		0	0	0	0	0	ZAn	off2		Zd				0
								size<1>	size<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	1	0	0	0	0	1	1	0	V	Rs		0	0	0	0	0	ZAn		o1	Zd				0
								size<1>	size<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	0	1	1	0	0	0	1	1	0	V	Rs		0	0	0	0	0	ZAn			Zd				0
								size<1>	size<0>