MOVA (vector to tile, four registers)

Move four vector registers to four ZA tile slices

The instruction operates on four consecutive horizontal or vertical slices within a named ZA tile of the specified element size.

The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 4 in the range 0 to the number of elements in a 128-bit vector segment minus 4.

This instruction is unpredicated.

This instruction is used by the alias MOV (vector to tile, four registers).

It has encodings from 4 classes: 8-bit , 16-bit , 32-bit and 64-bit

8-bit
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000000000100VRs001Zn00000off2
size<1>size<0>

MOVA ZA0<HV>.B[<Ws>, <offs1>:<offs4>], { <Zn1>.B-<Zn4>.B }

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 4; constant integer esize = 8; integer n = UInt(Zn:'00'); integer d = 0; integer offset = UInt(off2:'00'); boolean vertical = V == '1';

16-bit
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000001000100VRs001Zn00000ZAdo1
size<1>size<0>

MOVA <ZAd><HV>.H[<Ws>, <offs1>:<offs4>], { <Zn1>.H-<Zn4>.H }

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 4; constant integer esize = 16; integer n = UInt(Zn:'00'); integer d = UInt(ZAd); integer offset = UInt(o1:'00'); boolean vertical = V == '1';

32-bit
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000010000100VRs001Zn00000ZAd
size<1>size<0>

MOVA <ZAd><HV>.S[<Ws>, <offs1>:<offs4>], { <Zn1>.S-<Zn4>.S }

if !HaveSME2() then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 4; constant integer esize = 32; integer n = UInt(Zn:'00'); integer d = UInt(ZAd); integer offset = 0; boolean vertical = V == '1';

64-bit
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000011000100VRs001Zn0000ZAd
size<1>size<0>

MOVA <ZAd><HV>.D[<Ws>, <offs1>:<offs4>], { <Zn1>.D-<Zn4>.D }

if !HaveSME2() then UNDEFINED; if MaxImplementedSVL() < 256 then UNDEFINED; integer s = UInt('011':Rs); constant integer nreg = 4; constant integer esize = 64; integer n = UInt(Zn:'00'); integer d = UInt(ZAd); integer offset = 0; boolean vertical = V == '1';

Assembler Symbols

<ZAd>

For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAd" field.

For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAd" field.

For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAd" field.

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V <HV>
0 H
1 V
<Ws>

Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs1>

For the 8-bit variant: is the first slice index offset, encoded as "off2" field times 4.

For the 16-bit variant: is the first slice index offset, encoded as "o1" field times 4.

For the 32-bit and 64-bit variant: is the first slice index offset, with implicit value 0.

<offs4>

For the 8-bit variant: is the fourth slice index offset, encoded as "off2" field times 4 plus 3.

For the 16-bit variant: is the fourth slice index offset, encoded as "o1" field times 4 plus 3.

For the 32-bit and 64-bit variant: is the fourth slice index offset, with implicit value 3.

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Zn4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; if nreg == 4 && esize == 64 && VL < 256 then UNDEFINED; integer slices = VL DIV esize; bits(32) index = X[s, 32]; integer slice = ((UInt(index) - (UInt(index) MOD nreg)) + offset) MOD slices; for r = 0 to nreg-1 bits(VL) result = Z[n + r, VL]; ZAslice[d, esize, vertical, slice + r, VL] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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