MVN -- A64

Bitwise NOT writes the bitwise inverse of a register value to the destination register.

is equivalent to

and is always the preferred disassembly.

is equivalent to

and is always the preferred disassembly.

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wm>	Is the 32-bit name of the general-purpose source register, encoded in the "Rm" field.

<shift>

Is the optional shift to be applied to the final source, defaulting to LSL and encoded in shift:

<amount>	For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
	For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xm>	Is the 64-bit name of the general-purpose source register, encoded in the "Rm" field.

The description of ORN (shifted register) gives the operational pseudocode for this instruction.

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46