Move predicate from vector
Copy a packed bitmap, where bit value 0b1 represents TRUE and bit value 0b0 represents FALSE, from a portion of the source vector register to elements of the destination SVE predicate register.
Because the number of bits in an SVE predicate element scales with the vector element size, the behavior varies according to the specified element size.
The portion index is optional, defaulting to 0 if omitted.
It has encodings from 4 classes: Byte , Doubleword , Halfword and Word
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | 0 | Pd |
if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Pd); constant integer esize = 8; constant integer imm = 0;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | i3h | 1 | 0 | 1 | i3l | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | 0 | Pd |
if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Pd); constant integer esize = 64; constant integer imm = UInt(i3h:i3l);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | i1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | 0 | Pd |
if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Pd); constant integer esize = 16; constant integer imm = UInt(i1);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | i2 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | 0 | Pd |
if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Pd); constant integer esize = 32; constant integer imm = UInt(i2);
<Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
<Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(VL) operand = Z[n, VL]; bits(PL) result; constant integer psize = esize DIV 8; for e = 0 to elements-1 Elem[result, e, psize] = ZeroExtend(operand<(elements * imm) + e>, psize); P[d, PL] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.