Contiguous prefetch halfwords (immediate index)
Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address.
The predicate may be used to suppress prefetches from unwanted addresses.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | imm6 | 0 | 0 | 1 | Pg | Rn | 0 | prfop | ||||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 16; integer g = UInt(Pg); integer n = UInt(Rn); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 1; integer offset = SInt(imm6);
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(64) base; if AnyActiveElement(mask, esize) then base = if n == 31 then SP[] else X[n, 64]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then integer eoff = (offset * elements) + e; bits(64) addr = base + (eoff << scale); Hint_Prefetch(addr, pref_hint, level, stream);
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.