Predicate select between predicate register or all-false
If the indexed element of the second source predicate is true, place the contents of the first source predicate register into the destination predicate register, otherwise set the destination predicate to all-false. The indexed element is determined by the sum of a general-purpose index register and an immediate, modulo the number of elements. Does not set the condition flags.
For programmer convenience, an assembler must also accept predicate-as-counter register names for the destination predicate register and the first source predicate register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | i1 | tszh | 1 | tszl | Rv | 0 | 1 | Pn | 0 | Pm | 0 | Pd | ||||||||||||
| S | |||||||||||||||||||||||||||||||
if !HaveSME() && !HaveSVE2p1() then UNDEFINED; bits(5) imm5 = i1:tszh:tszl; integer esize; integer imm; case tszh:tszl of when '0000' UNDEFINED; when '1000' esize = 64; imm = UInt(imm5<4>); when 'x100' esize = 32; imm = UInt(imm5<4:3>); when 'xx10' esize = 16; imm = UInt(imm5<4:2>); when 'xxx1' esize = 8; imm = UInt(imm5<4:1>); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer v = UInt('011':Rv);
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
| <Pm> |
Is the name of the second source scalable predicate register, encoded in the "Pm" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Wv> |
Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field. |
| <imm> |
Is the element index, in the range 0 to one less than the number of vector elements in a 128-bit vector register, encoded in "i1:tszh:tszl". |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) operand1 = P[n, PL]; bits(PL) operand2 = P[m, PL]; bits(32) idx = X[v, 32]; integer element = (UInt(idx) + imm) MOD elements; bits(PL) result; if ActivePredicateElement(operand2, element, esize) then result = operand1; else result = Zeros(PL); P[d, PL] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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