RDFFR (predicated)

Return predicate of succesfully loaded elements

Read the first-fault register (FFR) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

313029282726252423222120191817161514131211109876543210
00100101000110001111000Pg0Pd
S

RDFFR <Pd>.B, <Pg>/Z

if !HaveSVE() then UNDEFINED; integer g = UInt(Pg); integer d = UInt(Pd); boolean setflags = FALSE;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pg>

Is the name of the governing scalable predicate register, encoded in the "Pg" field.

Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; bits(PL) mask = P[g, PL]; bits(PL) ffr = FFR[PL]; bits(PL) result = ffr AND mask; if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, 8); P[d, PL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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