Signed reversed divide (predicated)
Signed reversed divide active elements of the second source vector by corresponding elements of the first source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | Pg | Zm | Zdn | |||||||||||
| R | U | ||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size IN {'0x'} then UNDEFINED; constant integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Zdn); integer m = UInt(Zm); boolean unsigned = FALSE;
| <Zdn> |
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(VL) operand1 = Z[dn, VL]; bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, e, esize], unsigned); if ActivePredicateElement(mask, e, esize) then integer element2 = Int(Elem[operand2, e, esize], unsigned); integer quotient; if element1 == 0 then quotient = 0; else quotient = RoundTowardsZero(Real(element2) / Real(element1)); Elem[result, e, esize] = quotient<esize-1:0>; else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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