SDOT (4-way, multiple vectors)

Multi-vector signed integer dot-product

The signed integer dot product instruction computes the dot product of four signed 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the two or four first source vectors and four signed 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the two or four second source vectors. The widened dot product result is destructively added to the corresponding 32-bit or 64-bit element of the ZA single-vector groups. The vector numbers forming the single-vector group within each half of or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.

It has encodings from 2 classes: Two ZA single-vectors and Four ZA single-vectors

Two ZA single-vectors
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; if sz == '1' && !HaveSMEI16I64() then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 32 << UInt(sz); integer n = UInt(Zn:'0'); integer m = UInt(Zm:'0'); integer offset = UInt(off3); constant integer nreg = 2;

Four ZA single-vectors
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; if sz == '1' && !HaveSMEI16I64() then UNDEFINED; integer v = UInt('010':Rv); constant integer esize = 32 << UInt(sz); integer n = UInt(Zn:'00'); integer m = UInt(Zm:'00'); integer offset = UInt(off3); constant integer nreg = 4;