Conditionally select elements from two vectors
Select elements from the first source vector where the corresponding vector select predicate element is true, and from the second source vector where the predicate element is false, placing them in the corresponding elements of the destination vector.
This instruction is used by the alias MOV (vector, predicated).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 1 | 1 | Pv | Zn | Zd | ||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); integer v = UInt(Pv); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pv> |
Is the name of the vector select predicate register, encoded in the "Pv" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
| Alias | Is preferred when |
|---|---|
| MOV (vector, predicated) | Zd == Zm |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[v, PL]; bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) operand2 = if AnyActiveElement(NOT(mask), esize) then Z[m, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = Elem[operand1, e, esize]; else Elem[result, e, esize] = Elem[operand2, e, esize]; Z[d, VL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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