SHA512 Hash update part 1 takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma1 and chi functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register.
This instruction is implemented only when FEAT_SHA512 is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | Rm | 1 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||||
| O | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SHA512) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm);
| <Qd> |
Is the 128-bit name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Qn> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vtmp; bits(64) MSigma1; bits(64) tmp; bits(128) x = V[n, 128]; bits(128) y = V[m, 128]; bits(128) w = V[d, 128]; MSigma1 = ROR(y<127:64>, 14) EOR ROR(y<127:64>, 18) EOR ROR(y<127:64>, 41); Vtmp<127:64> = (y<127:64> AND x<63:0>) EOR (NOT(y<127:64>) AND x<127:64>); Vtmp<127:64> = (Vtmp<127:64> + MSigma1 + w<127:64>); tmp = Vtmp<127:64> + y<63:0>; MSigma1 = ROR(tmp, 14) EOR ROR(tmp, 18) EOR ROR(tmp, 41); Vtmp<63:0> = (tmp AND y<127:64>) EOR (NOT(tmp) AND x<63:0>); Vtmp<63:0> = (Vtmp<63:0> + MSigma1 + w<63:0>); V[d, 128] = Vtmp;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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