SHL

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
0101111101xxximmb010101RnRd
Uimmhopcode

SHL D<d>, D<n>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; constant integer esize = 8 << 3; constant integer datasize = esize; integer elements = 1; integer shift = UInt(immh:immb) - esize;

Vector

313029282726252423222120191817161514131211109876543210
0Q0011110!= 0000immb010101RnRd
Uimmhopcode

SHL <Vd>.<T>, <Vn>.<T>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; integer shift = UInt(immh:immb) - esize;

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the scalar variant: is the left shift amount, in the range 0 to 63, encoded as UInt("immh:immb") - 64.

For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1, encoded in immh:immb:

immh <shift>
0001 UInt(immh:immb) - 8
001x UInt(immh:immb) - 16
01xx UInt(immh:immb) - 32
1xxx UInt(immh:immb) - 64
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in immh:Q:

immh Q <T>
0001 0 8B
0001 1 16B
001x 0 4H
001x 1 8H
01xx 0 2S
01xx 1 4S
1xxx 0 RESERVED
1xxx 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d, datasize] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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