SHRNB

Shift right narrow by immediate (bottom)

Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

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010001010tszh1tszlimm3000100ZnZd
URT

SHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>

if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(3) tsize = tszh:tszl; if tsize == '000' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); integer n = UInt(Zn); integer d = UInt(Zd); integer shift = (2 * esize) - UInt(tsize:imm3);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <T>
0 00 RESERVED
0 01 B
0 1x H
1 xx S
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <Tb>
0 00 RESERVED
0 01 H
0 1x S
1 xx D
<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV (2 * esize); bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 bits(2*esize) element = Elem[operand, e, 2*esize]; integer res = UInt(element) >> shift; Elem[result, 2*e + 0, esize] = res<esize-1:0>; Elem[result, 2*e + 1, esize] = Zeros(esize); Z[d, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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