SMAX (multiple vectors)

Determine the signed maximum of elements of the two or four second source vectors and the corresponding elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors.

Two registers
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer dn = UInt(Zdn:'0'); integer m = UInt(Zm:'0'); constant integer nreg = 2; boolean unsigned = FALSE;

Four registers
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer dn = UInt(Zdn:'00'); integer m = UInt(Zm:'00'); constant integer nreg = 4; boolean unsigned = FALSE;

Assembler Symbols

<Zdn1>	For the two registers variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
	For the four registers variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<Zdn4>

Is the name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.

<Zdn2>

Is the name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.

<Zm1>	For the two registers variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.
	For the four registers variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.

<Zm4>

Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.

<Zm2>

Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; array [0..3] of bits(VL) results; for r = 0 to nreg-1 bits(VL) operand1 = Z[dn+r, VL]; bits(VL) operand2 = Z[m+r, VL]; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, e, esize], unsigned); integer element2 = Int(Elem[operand2, e, esize], unsigned); integer res = Max(element1, element2); Elem[results[r], e, esize] = res<esize-1:0>; for r = 0 to nreg-1 Z[dn+r, VL] = results[r];

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	1	size		1	Zm				0	1	0	1	1	0	0	0	0	0	0	0	Zdn				0
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31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	1	size		1	Zm			0	0	1	0	1	1	1	0	0	0	0	0	0	Zdn			0	0
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