Multi-vector signed saturating unsigned extract narrow
Saturate the signed integer value in each element of the four source vectors to unsigned integer value that is quarter the original source element width, and place the results in the quarter-width destination elements.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | sz | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | ||||||
| N | U | ||||||||||||||||||||||||||||||
if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(sz); integer n = UInt(Zn:'00'); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (4 * esize); bits(VL) result; for r = 0 to 3 bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 integer element = SInt(Elem[operand, e, 4 * esize]); Elem[result, r*elements + e, esize] = UnsignedSat(element, esize); Z[d, VL] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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