SQRDMULH (indexed)

Signed saturating rounding doubling multiply high (indexed)

Multiply all signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment, double and place the most significant rounded half of the result in the corresponding elements of the destination vector register. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1.

The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 1 to 3 bits depending on the size of the element.

It has encodings from 3 classes: 16-bit , 32-bit and 64-bit

16-bit

313029282726252423222120191817161514131211109876543210
010001000i3h1i3lZm111101ZnZd
R

SQRDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>]

if !HaveSVE2() && !HaveSME() then UNDEFINED; constant integer esize = 16; integer index = UInt(i3h:i3l); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

32-bit

313029282726252423222120191817161514131211109876543210
01000100101i2Zm111101ZnZd
size<1>size<0>R

SQRDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>]

if !HaveSVE2() && !HaveSME() then UNDEFINED; constant integer esize = 32; integer index = UInt(i2); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

64-bit

313029282726252423222120191817161514131211109876543210
01000100111i1Zm111101ZnZd
size<1>size<0>R

SQRDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>]

if !HaveSVE2() && !HaveSME() then UNDEFINED; constant integer esize = 64; integer index = UInt(i1); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

For the 16-bit and 32-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

For the 64-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<imm>

For the 16-bit variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

For the 32-bit variant: is the element index, in the range 0 to 3, encoded in the "i2" field.

For the 64-bit variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer eltspersegment = 128 DIV esize; bits(VL) operand1 = Z[n, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) result; for e = 0 to elements-1 integer segmentbase = e - (e MOD eltspersegment); integer s = segmentbase + index; integer element1 = SInt(Elem[operand1, e, esize]); integer element2 = SInt(Elem[operand2, s, esize]); integer res = 2 * element1 * element2; Elem[result, e, esize] = SignedSat((res + (1 << (esize - 1))) >> esize, esize); Z[d, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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