Signed saturating unsigned extract narrow (top)
Saturate the signed integer value in each source element to an unsigned integer value that is half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Zn | Zd | |||||||||
| T | |||||||||||||||||||||||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(3) tsize = tszh:tszl; integer esize; case tsize of when '001' esize = 16; when '010' esize = 32; when '100' esize = 64; otherwise UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(VL) operand1 = Z[n, VL]; bits(VL) result = Z[d, VL]; constant integer halfesize = esize DIV 2; for e = 0 to elements-1 integer element1 = SInt(Elem[operand1, e, esize]); bits(halfesize) res = UnsignedSat(element1, halfesize); Elem[result, 2*e + 1, halfesize] = res; Z[d, VL] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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