bits(2) scale = opcode<2:1>; integer selem = UInt(opcode<0>:R) + 1; boolean replicate = FALSE; integer index; case scale of when '11' // load and replicate if L == '0' || S == '1' then UNDEFINED; scale = size; replicate = TRUE; when '00' index = UInt(Q:S:size); // B[0-15] when '01' if size<0> == '1' then UNDEFINED; index = UInt(Q:S:size<1>); // H[0-7] when '10' if size<1> == '1' then UNDEFINED; if size<0> == '0' then index = UInt(Q:S); // S[0-3] else if S == '1' then UNDEFINED; index = UInt(Q); // D[0-1] scale = '11'; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; constant integer datasize = 64 << UInt(Q); constant integer esize = 8 << UInt(scale);

CheckFPAdvSIMDEnabled64(); bits(64) address; bits(64) eaddr; bits(64) offs; bits(128) rval; bits(esize) element; constant integer ebytes = esize DIV 8; AccessDescriptor accdesc = CreateAccDescASIMD(memop, nontemporal, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; offs = Zeros(64); if replicate then // load and replicate to all elements for s = 0 to selem-1 eaddr = GenerateAddress(address, offs, accdesc); element = Mem[eaddr, ebytes, accdesc]; // replicate to fill 128- or 64-bit register V[t, datasize] = Replicate(element, datasize DIV esize); offs = offs + ebytes; t = (t + 1) MOD 32; else // load/store one element per register for s = 0 to selem-1 rval = V[t, 128]; eaddr = GenerateAddress(address, offs, accdesc); if memop == MemOp_LOAD then // insert into one lane of 128-bit register Elem[rval, index, esize] = Mem[eaddr, ebytes, accdesc]; V[t, 128] = rval; else // memop == MemOp_STORE // extract from one lane of 128-bit register Mem[eaddr, ebytes, accdesc] = Elem[rval, index, esize]; offs = offs + ebytes; t = (t + 1) MOD 32; if wback then if m != 31 then offs = X[m, 64]; address = GenerateAddress(address, offs, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;