Store predicate register
Store a predicate register to a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current predicate register size in bytes. This instruction is unpredicated.
The store is performed as contiguous byte accesses, each containing 8 consecutive predicate bits in ascending element order, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then a general-purpose base register must be aligned to 2 bytes.
For programmer convenience, an assembler must also accept a predicate-as-counter register name for the source predicate register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm9h | 0 | 0 | 0 | imm9l | Rn | 0 | Pt | ||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Pt); integer n = UInt(Rn); integer imm = SInt(imm9h:imm9l);
| <Pt> |
Is the name of the scalable predicate transfer register, encoded in the "Pt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. |
CheckSVEEnabled(); constant integer PL = CurrentVL DIV 8; constant integer elements = PL DIV 8; bits(PL) src; bits(64) base; integer offset = imm * elements; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = n != 31; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; src = P[t, PL]; bits(64) addr = GenerateAddress(base, offset, accdesc); boolean aligned = IsAligned(addr, 2); if !aligned && AlignmentEnforced() then AArch64.Abort(addr, AlignmentFault(accdesc)); for e = 0 to elements-1 AArch64.MemSingle[addr, 1, accdesc, aligned] = Elem[src, e, 8]; offset = offset + 1; addr = GenerateAddress(base, offset, accdesc);
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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