Store Register (register) calculates an address from a base register value and an offset register value, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. For information about memory accesses, see Load/Store addressing modes.
The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Rm | option | S | 1 | 0 | Rn | Rt | ||||||||||||||
| size | VR | opc | |||||||||||||||||||||||||||||
integer scale = UInt(size); if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then scale else 0;
| <Wt> |
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Wm> |
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field. |
| <Xm> |
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field. |
| <amount> |
For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
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For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
|
| <Xt> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
integer n = UInt(Rn); integer t = UInt(Rt); integer m = UInt(Rm); constant integer datasize = 8 << scale;
bits(64) offset = ExtendReg(m, extend_type, shift, 64); bits(64) address; bits(datasize) data; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, TRUE); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = GenerateAddress(address, offset, accdesc); data = X[t, datasize]; Mem[address, datasize DIV 8, accdesc] = data;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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