STRH (immediate)

Store Register Halfword (immediate) stores the least significant halfword of a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset

Post-index

313029282726252423222120191817161514131211109876543210
01111000000imm901RnRt
sizeVRopc

STRH <Wt>, [<Xn|SP>], #<simm>

boolean wback = TRUE; boolean postindex = TRUE; bits(64) offset = SignExtend(imm9, 64);

Pre-index

313029282726252423222120191817161514131211109876543210
01111000000imm911RnRt
sizeVRopc

STRH <Wt>, [<Xn|SP>, #<simm>]!

boolean wback = TRUE; boolean postindex = FALSE; bits(64) offset = SignExtend(imm9, 64);

Unsigned offset

313029282726252423222120191817161514131211109876543210
0111100100imm12RnRt
sizeVRopc

STRH <Wt>, [<Xn|SP>{, #<pimm>}]

boolean wback = FALSE; boolean postindex = FALSE; bits(64) offset = LSL(ZeroExtend(imm12, 64), 1);

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly STRH (immediate).

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<pimm>

Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); boolean tagchecked = wback || n != 31; boolean rt_unknown = FALSE; Constraint c; if wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

Operation

bits(64) address; bits(16) data; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = GenerateAddress(address, offset, accdesc); if rt_unknown then data = bits(16) UNKNOWN; else data = X[t, 16]; Mem[address, 2, accdesc] = data; if wback then if postindex then address = GenerateAddress(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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