Subtract (shifted register), setting flags, subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.
This instruction is used by the aliases CMP (shifted register), and NEGS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 1 | 1 | 0 | 1 | 0 | 1 | 1 | shift | 0 | Rm | imm6 | Rn | Rd | ||||||||||||||||||
op | S |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); constant integer datasize = 32 << UInt(sf); if shift == '11' then UNDEFINED; if sf == '0' && imm6<5> == '1' then UNDEFINED; ShiftType shift_type = DecodeShift(shift); integer shift_amount = UInt(imm6);
<Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> |
Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Wm> |
Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<shift> |
Is the optional shift type to be applied to the second source operand, defaulting to LSL and
encoded in
|
<Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> |
Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Xm> |
Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field. |
Alias | Is preferred when |
---|---|
CMP (shifted register) | Rd == '11111' |
NEGS | Rn == '11111' && Rd != '11111' |
bits(datasize) result; bits(datasize) operand1 = X[n, datasize]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize); bits(4) nzcv; operand2 = NOT(operand2); (result, nzcv) = AddWithCarry(operand1, operand2, '1'); PSTATE.<N,Z,C,V> = nzcv; X[d, datasize] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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