Swap halfword in memory atomically loads a 16-bit halfword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register.
For more information about memory ordering semantics, see Load-Acquire, Store-Release.
For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | A | R | 1 | Rs | 1 | 0 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||||||
| size | VR | o3 | opc | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSE) then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); boolean acquire = A == '1' && Rt != '11111'; boolean release = R == '1'; boolean tagchecked = n != 31;
| <Ws> |
Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field. |
| <Wt> |
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(16) data; bits(16) store_value; AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; store_value = X[s, 16]; bits(16) comparevalue = bits(16) UNKNOWN; // Irrelevant when not executing CAS data = MemAtomic(address, comparevalue, store_value, accdesc); X[t, 32] = ZeroExtend(data, 32);
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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