UMLAL (multiple and indexed vector)

Multi-vector unsigned integer multiply-add long by indexed element

This unsigned integer multiply-add long instruction multiplies each unsigned 16-bit element in the one, two, or four first source vectors with each unsigned 16-bit indexed element of the second source vector, widens each product to 32-bits and destructively adds these values to the corresponding 32-bit elements of the ZA double-vector groups.

The elements within the second source vector are specified using an immediate element index which selects the same element position within each 128-bit vector segment. The index range is from 0 to 7, encoded in 3 bits. The lowest of the two consecutive vector numbers forming the double-vector group within all of, each half of, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

It has encodings from 3 classes: One ZA double-vector , Two ZA double-vectors and Four ZA double-vectors

One ZA double-vector
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
110000011100Zmi3hRv1i3lZn10off3
US

UMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]

if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(off3:'0'); integer index = UInt(i3h:i3l); constant integer nreg = 1;

Two ZA double-vectors
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv1i3hZn010i3loff2
US

UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]

if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn:'0'); integer m = UInt('0':Zm); integer offset = UInt(off2:'0'); integer index = UInt(i3h:i3l); constant integer nreg = 2;

Four ZA double-vectors
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
110000011101Zm1Rv1i3hZn0010i3loff2
US

UMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]

if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn:'00'); integer m = UInt('0':Zm); integer offset = UInt(off2:'0'); integer index = UInt(i3h:i3l); constant integer nreg = 4;

Assembler Symbols

<Wv>

Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs1>

For the one ZA double-vector variant: is the first vector select offset, encoded as "off3" field times 2.

For the four ZA double-vectors and two ZA double-vectors variant: is the first vector select offset, encoded as "off2" field times 2.

<offs2>

For the one ZA double-vector variant: is the second vector select offset, encoded as "off3" field times 2 plus 1.

For the four ZA double-vectors and two ZA double-vectors variant: is the second vector select offset, encoded as "off2" field times 2 plus 1.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zn1>

For the two ZA double-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.

For the four ZA double-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn4>

Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm>

Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<index>

Is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

Operation

CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; integer vectors = VL DIV 8; integer vstride = vectors DIV nreg; integer eltspersegment = 128 DIV esize; bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; vec = vec - (vec MOD 2); for r = 0 to nreg-1 bits(VL) operand1 = Z[n+r, VL]; bits(VL) operand2 = Z[m, VL]; for i = 0 to 1 bits(VL) operand3 = ZAvector[vec + i, VL]; for e = 0 to elements-1 integer segmentbase = e - (e MOD eltspersegment); integer s = 2 * segmentbase + index; integer element1 = UInt(Elem[operand1, 2 * e + i, esize DIV 2]); integer element2 = UInt(Elem[operand2, s, esize DIV 2]); bits(esize) product = (element1 * element2)<esize-1:0>; Elem[result, e, esize] = Elem[operand3, e, esize] + product; ZAvector[vec + i, VL] = result; vec = vec + vstride;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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