USMLALL (multiple and single vector)

Multi-vector unsigned by signed integer multiply-add long-long by vector

This unsigned by signed integer multiply-add long-long instruction multiplies each unsigned 8-bit element in the one, two, or four first source vectors with each signed 8-bit element in the second source vector, widens each product to 32-bits and destructively adds these values to the corresponding 32-bit elements of the ZA quad-vector groups. The lowest of the four consecutive vector numbers forming the quad-vector group within all of, each half of, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

It has encodings from 3 classes: One ZA quad-vector , Two ZA quad-vectors and Four ZA quad-vectors

One ZA quad-vector
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(off2:'00'); constant integer nreg = 1;

Two ZA quad-vectors
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(o1:'00'); constant integer nreg = 2;

Four ZA quad-vectors
(FEAT_SME2)

if !HaveSME2() then UNDEFINED; constant integer esize = 32; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(o1:'00'); constant integer nreg = 4;