Concatenate elements from four vectors
Concatenate every fourth element from each of the four source vectors and place them in the corresponding elements of the four destination vectors.
This instruction is unpredicated.
It has encodings from 2 classes: 8-bit to 64-bit elements and 128-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 1 | 0 | |||||
if !HaveSME2() then UNDEFINED; if size == '11' && MaxImplementedSVL() < 256 then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn:'00'); integer d = UInt(Zd:'00');
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 1 | 0 | ||||
if !HaveSME2() then UNDEFINED; if MaxImplementedSVL() < 512 then UNDEFINED; constant integer esize = 128; integer n = UInt(Zn:'00'); integer d = UInt(Zd:'00');
| <Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4. |
| <T> |
Is the size specifier,
encoded in
|
| <Zd4> |
Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. |
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 4 then UNDEFINED; constant integer quads = VL DIV (esize * 4); bits(VL) result0; bits(VL) result1; bits(VL) result2; bits(VL) result3; for r = 0 to 3 bits(VL) operand = Z[n+r, VL]; integer base = r * quads; for q = 0 to quads-1 Elem[result0, base+q, esize] = Elem[operand, 4*q+0, esize]; Elem[result1, base+q, esize] = Elem[operand, 4*q+1, esize]; Elem[result2, base+q, esize] = Elem[operand, 4*q+2, esize]; Elem[result3, base+q, esize] = Elem[operand, 4*q+3, esize]; Z[d+0, VL] = result0; Z[d+1, VL] = result1; Z[d+2, VL] = result2; Z[d+3, VL] = result3;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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