UZP (two registers)

Concatenate elements from two vectors

Concatenate every second element from each of the first and second source vectors and place them in the corresponding elements of the two destination vectors.

This instruction is unpredicated.

It has encodings from 2 classes: 8-bit to 64-bit elements and 128-bit element

8-bit to 64-bit elements
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size1Zm110100ZnZd1

UZP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>

if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd:'0');

128-bit element
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001001Zm110101ZnZd1

UZP { <Zd1>.Q-<Zd2>.Q }, <Zn>.Q, <Zm>.Q

if !HaveSME2() then UNDEFINED; if MaxImplementedSVL() < 256 then UNDEFINED; constant integer esize = 128; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd:'0');

Assembler Symbols

<Zd1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 2 then UNDEFINED; constant integer pairs = VL DIV (esize * 2); bits(VL) result0; bits(VL) result1; for r = 0 to 1 integer base = r * pairs; bits(VL) operand = if r == 0 then Z[n, VL] else Z[m, VL]; for p = 0 to pairs-1 Elem[result0, base+p, esize] = Elem[operand, 2*p+0, esize]; Elem[result1, base+p, esize] = Elem[operand, 2*p+1, esize]; Z[d+0, VL] = result0; Z[d+1, VL] = result1;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.