WHILEGE (predicate)

Generate a predicate that starting from the highest numbered element is true while the decrementing value of the first, signed scalar operand is greater than or equal to the second scalar operand and false thereafter down to the lowest numbered element.

If the second scalar operand is equal to the minimum signed integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate.

The full width of the scalar operands is significant for the purposes of comparison, and the full width first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated.

The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

if !HaveSVE2() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer rsize = 32 << UInt(sf); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Pd); boolean unsigned = FALSE; SVECmp op = Cmp_GE;

Assembler Symbols

<Pd>	Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<R>

Is a width specifier, encoded in sf:

sf	<R>
0	W
1	X

<n>	Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.

<m>	Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = Ones(PL); bits(rsize) operand1 = X[n, rsize]; bits(rsize) operand2 = X[m, rsize]; bits(PL) result; boolean last = TRUE; constant integer psize = esize DIV 8; for e = elements-1 downto 0 boolean cond; case op of when Cmp_GT cond = (Int(operand1, unsigned) > Int(operand2, unsigned)); when Cmp_GE cond = (Int(operand1, unsigned) >= Int(operand2, unsigned)); last = last && cond; bit pbit = if last then '1' else '0'; Elem[result, e, psize] = ZeroExtend(pbit, psize); operand1 = operand1 - 1; PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d, PL] = result;

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46