IC -- A64

IC

Instruction cache operation

For more information, see op0 == 0b01, cache maintenance, TLB maintenance, address translation, prediction restriction, BRBE, Trace Extension, and Guarded Control Stack instructions.

This is an alias of SYS. This means:

The encodings in this description are named to match the encodings of SYS.
The description of SYS gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			0	1	1	1	CRm				op2			Rt
										L						CRn

Encoding

IC <ic_op>{, <Xt>}

is equivalent to

SYS #<op1>, C7, <Cm>, #<op2>{, <Xt>}

and is the preferred disassembly when SysOp(op1, '0111', CRm, op2) == Sys_IC.

Assembler Symbols

<ic_op>

Is an IC operation name, as listed for the IC system instruction pages, encoded in (op1 :: CRm :: op2):

op1	CRm	op2	<ic_op>	Description
000	0001	000	IALLUIS	For more information, see IC IALLUIS.
000	0101	000	IALLU	For more information, see IC IALLU.
011	0101	001	IVAU	For more information, see IC IVAU.

<Xt>	Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

Operation

The description of SYS gives the operational pseudocode for this instruction.

2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.